1. Field of the Invention
The present invention relates to an image information processing apparatus for processing image information.
2. Related Background Art
As an image information processing apparatus for processing image information, a data communication system that transmits/receives image data is known.
FIG. 1 is a block diagram showing the arrangement of a conventional data communication system. Referring to FIG. 1, a transmission apparatus 100a and a receiving apparatus 200a constitute the data communication system.
The transmission apparatus 100a comprises an A/D converter 1a for converting a video signal input from an image input device such as a camera into digital data. The apparatus 100a also comprises a memory 2a for temporarily storing digital data and a D/A converter 3a for converting digital data into analog data.
The apparatus 100a further comprises transmission buffers 4a, 5a, and 6a for respectively performing impedance matching of communication lines 9a, 10a, and 11a, a memory controller 7a for controlling data read/write accesses to the memory 2a, and a clock generator 8a for generating clocks to be supplied to the A/D converter 1a, the D/A converter 3a, and the memory 2a. The apparatus 100a is connected to the receiving apparatus 200a via the communication lines 9a, 10a, and 11a.
The receiving apparatus 200a comprises reception buffers 12a, 13a, and 14a for respectively performing impedance matching of the communication lines 9a, 10a, and 11a, a clamp circuit 15a for converting a signal into a level suitable for an A/D converter 16a on its output side, and a memory 17a for temporarily storing received data.
The operation of the data communication system will be described below. A video signal input to the A/D converter 1a is converted by the A/D converter 1a into a digital signal. The converted digital signal is input to and temporarily stored in the memory 2a. Note that digital data can be directly input to the memory 2a using an external device.
The memory controller 7a controls the read/write accesses to the memory 2a in accordance with a user's request. The memory 2a, the read/write accesses to which are controlled by the memory controller 7a, outputs data according to the user's request. Data output from the memory 2a is input to the D/A converter 3a, and is converted into an analog signal.
The clock generator 8a outputs clocks for performing A/D conversion to the A/D converter 1a, clocks for controlling the read/write accesses to the memory 2a, and clocks for performing D/A conversion to the D/A converter 3a.
The analog signal D/A-converted by the D/A converter 3a is input to the transmission buffer 4a. The transmission buffer 4a performs impedance matching by amplifying the input analog signal by 6 dB, and sends the analog signal to the reception buffer 12a of the receiving apparatus 200a via the communication line 9a.
The clocks supplied to the A/D converter 1a, memory 2a, and D/A converter 3a are similarly input to the transmission buffer 5a. The transmission buffer 5a performs impedance matching by amplifying the clocks by 6 dB, and sends them to the reception buffer 13a via the communication line 10a.
The analog signal transmitted from the transmission buffer 4a is received by the reception buffer 12a. The clamp circuit 15a converts the received analog signal to a level suitable for A/D conversion. The signal clamped by the clamp circuit 15a is input to the A/D converter 16a, and is converted into a digital signal. The digital signal is then input to the memory 17a.
The clocks generated by the clock generator 8a are transmitted via the communication line 10a and are received by the reception buffer 13a. These clocks are supplied as those for the A/D converter 16a or those for storing data in the memory 17a.
On the other hand, data output from the memory 2a is sent to the reception buffer 14a via the communication line 11a. The reception buffer 14a outputs the data to the memory 17a and stores it therein.
FIG. 2 is a circuit diagram showing the arrangements of the transmission buffer 4a and the reception buffer 12a. Since the transmission buffer 5a and the reception buffer 13a respectively have the same arrangements as those of the transmission buffer 4a and the reception buffer 12a, a detailed description thereof will be omitted. Referring to FIG. 2, the transmission buffer 4a comprises a transmission operational amplifier 18a and a termination resistor 19a. Also, the buffer 4a comprises a feedback resistor Rf 20a and an input resistor Ri 21a. The reception buffer 13a comprises a termination resistor 22a and a reception operational amplifier 23a. A signal input to the transmission buffer 4a is input to the operational amplifier 18a. Note that the feedback resistor (Rf) 20a and the input resistor (Ri) 21a have the same resistance. At this time, the amplification factor of the operation amplifier 18a is 2.times., and a gain of 6 dB is obtained. The termination resistors 22a and 19a respectively have a resistance of 75 .OMEGA.. The signal output from the operational amplifier 18a is input to the operational amplifier 23a via the communication line 9a, which is terminated by the termination resistors 19a and 22a. The signal input to the reception operational amplifier 23a is amplified to a gain of 1.times. by a voltage-follower circuit, and is output to the next stage.
However, the conventional data communication system suffers the following problems. That is, in order to communicate signals such as data, clocks, and the like via the communication lines, the corresponding communication lines, transmission buffers, and reception buffers are required. As a consequence, the size of the data communication system increases, and the number of communication lines increases.
As another conventional image information processing apparatus, an image input apparatus, which fetches an image using a solid-state imaging element such as a CCD and outputs the image to display it on a monitor or to store it in a memory after digital conversion is known. FIG. 3 is a block diagram showing the arrangement of the conventional image input apparatus. Referring to FIG. 3, the apparatus comprises a lens 1201, an aperture portion 1202, an optical low-pass filter 1203 with a complementary color mosaic pattern, a CCD 1204, a gain amplifier 1205, and an A/D conversion circuit 1206.
The apparatus also comprises a memory A 1207, a memory B 1208, an operation processing circuit 1209, a selector 1210, a look-up table (LUT) 1211, a D/A conversion circuit 1212, a memory controller 1213, a CPU 1214, and a timing generator 1215.
In the image input apparatus with the above-mentioned arrangement, an image signal input via the lens 1201 passes through the aperture portion 1202 and the optical low-pass filter 1203, and is supplied to the CCD 1204. A charge accumulated on the CCD 1204 is read out as an optical image electrical signal by driving the CCD 1204 in accordance with a control signal from the timing generator 1215, and the readout electrical signal is amplified by the gain amplifier 1205. Thereafter, the amplified electrical signal is output.
The gain amplifier 1205 is level-controlled by a signal from the timing generator 1215, which is controlled by the CPU 1214.
The output signal from the gain amplifier 1205 is converted into a digital signal by the A/D conversion circuit 1206, and is stored in the memory A 1207 as cyan (Cy), magenta (Mg), yellow (Ye), and green (G) data. On the other hand, the memory B 1208 stores dark signal data. The dark signal data is the one obtained from the CCD 1204 in the light-shielded state by closing the aperture portion 1202 upon resetting the system. The memories A 1207 and B 1208 are respectively controlled by the memory controller 1213.
The operation processing circuit 1209 subtracts the dark signal data read out from the memory B 1208 from the complementary color image data read out from the memory A 1207. The operation result is converted from cyan, magenta, and yellow data into a luminance signal (U) and color difference signals (Cr, Cb) by a matrix operation based on a 3.times.3 coefficient A given by the following equation (1): ##EQU1##
Data converted into the luminance signal and the color difference signals are supplied to the selector 1210. The selector 1210 is controlled by the CPU 1214. The selector 1211 determines one to be selected of some data tables of the subsequent LUT 1211.
FIG. 4 is a graph showing the .gamma. conversion table data of the LUT 1211. When this data table has some .gamma. curves, arbitrary outputs can be obtained. The table data may be those other than .gamma. conversion.
The output from the LUT 1211 is supplied to the D/A conversion circuit 1212, and is re-converted from digital data to analog data. The analog data is output as a video signal to an external circuit. The output video signal is directly displayed on a monitor or is stored at an arbitrary location after predetermined processing.
In the latter case, the video signal is processed as an analog signal or after it is converted into a digital signal. In the following description, an image processing apparatus that performs digital image processing will be briefly exemplified.
FIG. 5 is a block diagram showing the arrangement of an image processing apparatus. The image processing apparatus and the above-mentioned image input apparatus are connected via a signal line and a control line. Referring to FIG. 5, an input signal from the image input apparatus is converted into a digital signal by an A/D conversion circuit 1101, and the digital signal is supplied to a digital signal processing circuit 1103 or a switch 1107. When an input image data is stored in a memory 1110 through the switch 1107, it is written in the memory 1110 controlled by a memory controller 1106. Similarly, the read control of the memory 1110 is performed by the memory controller 1106.
On the other hand, the digital signal processing circuit 1103 is a circuit for converting the luminance signal and the color difference signals into R, G, and B signals or a circuit for performing digital operation processing. When the output from the digital signal processing circuit 1103 is selected by the switch 1107, the processed data is written in the memory 1110.
However, although the conventional image processing apparatus processes a digital signal as in the image input apparatus, input/output units that connect the two apparatuses transmit/receive an analog signal. Therefore, upon digital-to-analog (D/A) conversion and analog-to-digital (A/D) conversion for transmitting image data, the image data may deteriorate.
In order to solve this problem, when another input/output units that can exchange digital data are added, the number of parts of the apparatus increases to increase cost, and the number of processing steps increases.
Image data may be transferred using the control line. However, the control line is not suitable for transferring the image data since it has a maximum data transfer rate of 1 to 2 Mbps.